1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing, and more specifically to the field of chemical-mechanical polishing methods and apparatuses for the planarization and removal of thin films used in semiconductor manufacturing.
2. Description of Relevant Art
Integrated circuits manufactured today are made up of literally millions of active devices such as transistors and capacitors formed in a semiconductor substrate. Integrated circuits rely upon an elaborate system of metalization in order to connect the active devices into functional circuits. A typical multilevel interconnect 100 is shown in FIG. 1. Active devices such as MOS transistors 107 are formed in and on a silicon substrate or well 102. An interlayer dielectric (ILD) 104, such as SiO.sub.2, is formed over silicon substrate 102. ILD 104 is used to electrically isolate a first level of metalization which is typically aluminum from the active devices formed in substrate 102. Metalized contacts 106 electrically couple active devices formed in substrate 102 to the interconnections 108 of the first level of metalization. In a similar manner metal vias 112 electrically couple interconnections 114 of a second level of metalization to interconnections 108 of the first level of metalization. Contacts and vias 106 and 112 typically comprise a metal 116 such as tungsten (W) surrounded by a barrier metal 118 such as titanium-nitride (TiN). Additional ILD/contact and metalization layers can be stacked one upon the other to achieve the desired interconnection.
A considerable amount of effort in the manufacturing of modern complex, high density multilevel interconnections is devoted to the planarization of the individual layers of the interconnect structure. Nonplanar surfaces create poor optical resolution of subsequent photolithographic processing steps. Poor optical resolution prohibits the printing of high density lines. Another problem with nonplanar surface topography is the step coverage of subsequent metalization layers. If a step height is too large there is a serious danger that open circuits will be created. Planar interconnect surface layers are a must in the fabrication of modern high density integrated circuits.
To ensure planar topography, various planarization techniques have been developed. One approach, known as chemical-mechanical polishing, employs polishing to remove protruding steps formed along the upper surface of ILDs. Chemical-mechanical polishing is also used to "etch back" conformally deposited metal layers to form planar plugs or vias. In a typical chemical-mechanical polishing method, as shown in FIGS. 2a and 2b, a silicon substrate or wafer 202 is placed face down on a rotating table 204 covered with a flat pad 206 which has been coated 208 with an active slurry. A carrier 210 is used to apply a downward force F.sub.1 against the backside of substrate 202. The downward force F.sub.1 and the rotational movement of pad 206 together with the slurry facilitate the abrasive polishing or planar removal of the upper surface of the thin film. Carrier 210 is also typically rotated to enhance polishing uniformity.
There are several disadvantages associated with present techniques of chemical-mechanical polishing. One significant problem is the different pad environments seen by different radii of the wafer being polished. This problem is due to the rotational movement of pad 206. As is apparent in FIG. 2b, the radius of pad 206 is significantly larger than the radius of wafer 202. During polishing, polishing pad 206 becomes worn, and a polishing track 210 develops in polishing pad 206. Inner track 210b of polishing pad 206 wears out faster that outer track 210a of polishing pad 206 because there is less pad material along inner track 210b than outer track 210a. The uneven pad wear results in a degradation of polishing uniformity across a wafer and from wafer to wafer.
Another problem associated with present chemical-mechanical polishing techniques is the slurry delivery process. As shown in FIGS. 2a and 2b, slurry is simply dumped from a nozzle 208 onto pad 206. Slurry then rotates around on pad 206 and attempts to pass under the wafer 202 being polished. Unfortunately, however, slurry builds up on the outside of wafer 202 and creates a "squeegee effect" which results in poor slurry delivery to the center of the wafer. Such a nonuniform and random slurry delivery process creates a nonuniform polishing rate across a wafer and from wafer to wafer. It is to be appreciated that the polishing rate is proportional to the amount of slurry beneath the wafer during polishing.
Another problem with present slurry delivery systems is the long time it takes for slurry to reach wafer 206, pass beneath it, and finally polish. Such a long transition time prohibits a manufacturably reliable switching from one slurry to another, as may be desired in the case of polishing back a barrier metal after the polishing of a via filling metal. Additionally, some slurries degrade when exposed to air for extended periods of time. The polishing qualities of these slurries can degrade in present slurry delivery systems.
Additionally, present slurry deliver systems waste much of the slurrry that is used in the polishing process. This results in higher manufacturing costs. Excesssive slurry waste is especially problematic when expensive slurries, such as ceria slurries, are used. Each of these characteristics makes present slurry deliver techniques manufacturably unacceptable.
Thus, what is needed is a method of polishing thin films formed on a semiconductor substrate or wafer wherein polishing pad movement and slurry delivery are more uniform across the surface of a wafer so that thin films formed on the wafer surface exhibit a more uniform polish rate across the wafer and from wafer to wafer.